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Aldec IP
Aldec and its partners to provide reusable design IP core and verification IP ，which could be simulated by Aldec's Active-HDL and Riviera-PRO mixed-language simulator. These rich set of IP model library to promote system-level design and verification, and accelerate product time-to-market. For more…
Microtronix IP
All Microtronix IP core for Altera FPGA and hardcopy devices and ASIC applications undergo a rigorous testing and optimization. By an easy-to-use GUI, engineers can quickly instantiated parameterized IP module, it is particularly important to reduce design and test verification time. For more…
Campera Electronic Systems offers state-of-the-art high performance FPGA design services, including:
1. Radar IP library
The CES radar and sensor IP library is a modular collection of radar applications, fully parallel radar signal generators, circular convolution pulse compressors, channelizers and electronic countermeasures for high-performance parallel processing IP modules. System bandwidth exceeds system bandwidth. A few tens of GHz can greatly shorten the design verification time.More...
2. Video processing IP library
The CES video processing IP library is a collection of high-performance video and image processing modules. The video processing solution can meet the requirements of high resolution, high frame rate and ultra low latency. Proprietary algorithms and high-performance ASIP cores are available for FPGAs and SoCs to create powerful, flexible systems.More...
3. Extreme performance DSP application IP library
CES Extreme Performance DSP Application IP Library is a collection of DSP processing applications, including filtering (FIR, IIR, 1D, 2D, CIC, multirate filters), FFT (radix-2/4/8, Cooley-Tukey / Winograd) , DDC / DUC, DDS, and CORDIC, etc. Each module is designed to meet the needs of ultra-high performance applications to meet the extreme requirements of data rate, resource usage, power consumption and speed.More...
4. Mathematical operation IP core
The CES Math IP Library is a collection of FPGA math modules, including math, fixed-point and floating-point (single-precision or double-precision, IEEE-754-compliant) math VHDL modules, and supports real and complex data types as well as trigonometric functions. The CES Math IP Library is a high-quality VHDL code that is independent of the device manufacturer and comes with a test platform and documentation for self-testing.More...
5. FPGA design verification and technical services
CES has more than 10 years of FPGA design expertise and an extensive HDL library for security critical applications (DO-254), FPGA design, custom IP cores, and verification and verification services. Professional-based HDL development processes, coding standards and technologies reduce design risk and improve design quality.
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