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北京阿尔戴信息技术有限公司 has received tha national award as "FPGA Tool Outstanding Contribution Award for Year 2013 in China" 

Chengdu, Sichuan province, China – Jun 20, 2013 – Guidance by the Ministry of Industry and Information Technology, organized by the China Electronics News, Sichuan Institute of Electronics, and other contractors,"2013 (5th), China National FPGA Industry Development conference", held in Chengdu on Jun 20, 2013, 北京阿尔戴信息技术有限公司 has received the national award as  “FPGA Tool Outstanding Contribution Award for Year 2013 in China”.

Aldec launches Spec-TRACER™ – Requirements Lifecycle Management for Safety-critical FPGA and ASIC Designs

Certification Together International Conference (CTIC), Toulouse, France – May 20, 2013 – Aldec, Inc., CTIC Platinum Sponsor  and pioneer in mixed-language simulation and advanced design tools for FPGA and ASIC devices, today announces the launch of Spec-TRACER™, a new requirements lifecycle management solution for use in safety-critical industries in which rigorous certification standards exist; such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear.


Managing and recording how an FPGA or ASIC is developed against its requirements is an increasingly complex task, yet essential for certification and critical to produce high-quality, reliable, safe and compliant products.


“Spec-TRACER is exactly what the avionics industry needs to help satisfy the traceability objectives of DO-254,” said Louie De Luna, Aldec DO-254 Program Manager, “Ensuring that traceability exists throughout the entire development lifecycle is crucial to proving that the product has been designed and tested through a requirements-based process, from top-level design requirements to HDL source code, and from verification test cases to the testbench and through to the simulation results.”


Spec-TRACER helps organizations manage, control and track requirements efficiently throughout the entire FPGA/ASIC development lifecycle to help keep the project on track and within budget. It does this by streamlining and automating the requirements engineering process such as capture, traceability, requirements versions tracking, results management and reporting.


Features within the launch version of Spec-TRACER (2013.05) include: specification import (from MS Word, MS Excel and DOORS), change impact analysis, requirements coverage analysis; pre- and user-defined traceability reports, and multi-user access (which in team-based environments allows project stakeholders to collaborate and communicate more efficiently). In addition, traceability links between requirements, test plans and HDL source code are established easily and multi-directional traceability reports are generated automatically.


Aldec Presents at Military & Aerospace Programmable Logic Devices Symposium (MAPLD)

Henderson, NV – April 8, 2013 – Aldec, Inc. together with Microsemi, The Boeing Company, Northrop Grumman Corporation and other leading vendors, is scheduled to present at the Military and  Aerospace Programmable Logic Devices Symposium (MAPLD) in San Diego, CA from April 9-12, 2013.

MAPLD event will showcase leading research in the field of programmable devices for use in military and aerospace applications. Aldec will present on two separate Design and Verification topics that continue to provide a high level of interest from the military and aerospace community. For more

Aldec Releases Plot Window to Increase Productivity of Traditional Waveform-Based HDL Debugging

Henderson, NV – March 11, 2013 – Aldec, Inc. announces the latest release of its mixed-language advanced verification platform, Riviera-PRO™ 2013.02. This release includes numerous enhancements, including visual debugging tools that improve the presentation of simulation results for increased overall verification efficiency. Riviera-PRO 2013.02 includes a Plot window supporting four different plot types to enable more efficient visualization of large data sets, as well as the ability to visualize and analyze relations between any objects within a design with no additional programming required. For more

Hitachi Cable, Ltd. Deploys ALINT™ on Next Generation FPGA Design

Henderson, NV –  January 7, 2013 – Aldec, Inc., the leading provider of design creation and verification solutions for semiconductor industry, announced today that Hitachi Cable, Ltd., (head office: Tokyo, Japan; hereafter, “Hitachi Cable”), the leading developer of communication and transmission technologies for the information and energy sectors, has adopted ALINT™ as a part of the RTL review and validation process in their corporate FPGA design flow.


Hitachi Cable performed an extensive analysis of ALINT on one of their current designs targeting the largest FPGA available in the market today. The product achieved the required critical mass from the engineering divisions to be deployed in its FPGA design flow to ensure early bug detection, perform automated code reviews and enforce uniform RTL coding style across the organization.


"Based on a common fact that verification takes up to 70% of entire design cycle, we believe in starting verification tasks at the very early stages of design flow when cost and efficiency of fixing bugs are optimal", said Koichiro Seto, General Manager, Hitachi Cable Core Technology Dept. "Since we started using ALINT, we have identified several critical problems in our current RTL design, including complex hierarchical issues that would otherwise result in excessive routing delays. We also worked diligently with Aldec-Japan local Applications Team to deploy automated code reviews based on STARC rules and custom design policies tuned to detect issues critical to our environment. So far we have seen many positive indicators of Aldec products helping us to attain excellent results and lower overall development cost."


"We are pleased that Hitachi Cable has selected Aldec for their current and next generation FPGA designs, and we look forward to working further with Hitachi Cable as we expand our business in Japan", said Dmitry Melnik, Product Manager, Aldec Software Division. "With FPGA designs being no simpler than ASICs nowadays, we are seeing more and more interest for traditionally ASIC tools and design policies from FPGA design teams. Well-known for a large FPGA user base, Aldec has incorporated many features key to the FPGA designers into ALINT, including the unique support for FPGA vendor primitives, precompiled FPGA vendor libraries, and lowest false violation ratios, making the tool stand out from competition, which has been proven once again by Hitachi Cable adopting ALINT."

Aldec Emulation and Verification Tools Adopted by Taiwan National Chiao Tung University for ESL Design Master’s Program

Henderson, NV - January 2, 2013 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, today announced that Taiwan National Chiao Tung University has adopted Aldec’s emulation and verification tools for their new and innovative Master of Advanced Studies (MAS) Program in ESL Design. To provide the master’s program with world class commercial EDA products, Aldec will provide licenses for Riviera-PRO™ mixed-language simulation and verification platform and HES-EDU™ hardware-assisted verification.  


“Aldec is committed to education and we believe in the importance of educating both working and future engineers in leading-edge verification methodologies and tools,” said Dick Tao, Aldec Taiwan Country Manager, “For this reason Aldec is proud to invest in the success of this program by providing students with access to our latest tools.”


“The MAS Program in ESL Design allows professional engineers to take advantage of National Chiao Tung University world-renowned expertise in intelligent vision system & SoC design methodology,” said professor Jiun-In Guo, Graduate School Director of Electronics Engineering Department, National Chiao Tung University at Taiwan, “This program provides the students a unique opportunity to build complete, state-of-the-art ESL systems using advanced commercial tools and we consider Aldec design tools as integral to our program.”


“A model for master’s degrees in engineering, this program offers intense hands-on experience and training for the engineering talent of tomorrow in advanced laboratories with substantial guidance from working engineers,” added professor Jiun-In Guo. “We are grateful to Aldec, Andestech, Xilinx, and other companies for making such labs possible.”


About NCTU’s ESL Design Master’s Program

The NCTU School of Engineering recently launched an innovative new master’s degree program tailored to the needs of industry and engineering professionals. The MAS program in ESL Design allows students to gain a deep and broad education in the multidisciplinary fundamentals of image processing design and ESL Design.

Pico Computing Introduces New Products at Supercomputing 2011

Seattle, WA – November 14, 2011 – Pico Computing today announces the immediate availability of the EX-400 PCIe backplane. The EX-400, along with the recently released M-505, will be on display during the Supercomputing Conference being held in Seattle, WA, November 12th – 18th 2011

The EX-400 PCIe backplane is a fully switched PCIe modular solution, providing x8 Gen2 interface to four M-501/505s or two M-503/504s FPGA modules. With a shorter form-factor than the existing EX-500, this new board can fit into any size chassis. Add multiple EX-400s to your system and build a scalable FPGA cluster.

The M-505 Module is the latest in Pico’s line of M-Series modular FPGA cards for High-Performance Computing and embedded applications. This board features the Xilinx Kintex-7 K325T FPGA. Based on their 28nm fabrication process, the Kintex-7 achieves a 2x price/performance improvement while consuming 50% less power than previous generation FPGAs. The M-505 has one DDR3 SODIMM for up to 4GB of local RAM, x8 Gen2 PCIe, and 128MB of configuration FLASH. There are 34 LVDS and 8 GTX transceivers available for user I/O.


About Pico Computing

Pico Computing, headquartered in Seattle, Washington, specializes in highly integrated hardware accelerator platforms based on Field Programmable Gate Array (FPGA) technologies. We are hardware and embedded software design experts with domain knowledge in applications that include cryptography, networking, signal processing, bioinformatics, and scientific computing. Visit for more info.

Pico Computing Demonstrates Bioinformatics Acceleration at SC 2011

--Pico’sSC5 FPGA cluster reduces short read sequencing from 6½ hours to just one minute

Seattle, WA – November 9, 2011 – Pico Computing will be demonstrating an FPGA implementation of BFAST resulting in a 350X acceleration over a software–only implementation running on two quad core Intel Xeon processors. The 350X acceleration was achieved using 8 Pico M-503 FPGA modules in their SC5 SuperCluster chassis. The BFAST algorithm is primarily used in short read genome mapping.

The study of DNA has become computationally intensive to due to rapid improvements in both cost and throughput of next-generation sequencing machines. Scientists use these next-generation sequencing machines to replicate a DNA strand many times, randomly cut strands into short lengths, sequence the nucleotide bases of each length, and then compare against a known reference genome.

Next-generation sequencing machines are able to sequence the short pieces of DNA, which are called short reads, in a massively parallel fashion, leading to lower cost per genome and higher throughput per run. However, the process of mapping those short reads to a reference genome relies on software programs to search the three billion base-pair genome for places where each short read appears. The time required to complete this mapping phase is becoming the bottleneck for DNA studies, since CPUs are not able to exploit the inherent data parallelism in the search.

Pico Computing will be demonstrating the FPGA BFAST implementation at Supercomputing 2011 (SC11) November 14-18, 2011 in Seattle, Washington (booth #2300). In addition, Corey Olson will be giving a talk during SC11, titled: “FPGA Acceleration of Short Read Human Genome Mapping” at 4:30pm on Tuesday, November 15th in room WSCC 613/614.

The BFAST algorithm finds possible match locations for each short read in the genome and then Smith- Waterman is used to score each location. “FPGAs offer the potential for drastic improvement in the runtime of the mapping phase because we can greatly accelerate this searching process,” said Corey Olson, Senior Engineer at Pico Computing and developer of the BFAST implementation. “With a scalable FPGA system such as the M-503, we accelerate both the process of finding candidate alignment locations and the Smith-Waterman scoring.”


About Pico Computing

Pico Computing, headquartered in Seattle, Washington, specializes in highly integrated hardware accelerator platforms based on Field Programmable Gate Array (FPGA) technologies. We are hardware and embedded software design experts with domain knowledge in applications that include cryptography, networking, signal processing, bioinformatics, and scientific computing. Visit for more info.


Pico Computing Develops Xilinx Kintex-7 Module

--Modular FPGA board enables hardware--accelerated computing with reduced power consumption

Seattle, WA – November 7, 2011 – Pico Computing announced today the development of the M-505module, the first board to be released with the new Xilinx Kintex-7 FPGA, the world’s first shipping 28nm programmable logic device. The M-505 has been designed to be used in conjunction with Pico’s current EX-500 PCIe backplane giving users an easy upgrade path.

Kintex-7 FPGAs are the mid-range of Xilinx’s new 28nm 7-series families of FPGAs. All three families (Virtex-7, Kintex-7, and Artix-7), uses TSMC’s high-performance, low-power (HPL) 28nm process designed for power efficiency. This process delivers a 2x price/performance improvement while consuming 50% less power than previous generation FPGAs. “Pico is proud to be early to market with a board running the Kintex-7 series FPGA. The M-505 demonstrates our commitment to staying in the forefront of the industry,” said Kelley Dobelstein, Sr. Hardware Engineer for Pico Computing.

Since all 7 series FPGAs leverage Xilinx’s unified architecture, user IP investment is protected and migration from Virtex-6 designs is easy. The unified architecture facilitates rapid retargeting within the 7 series. Designs from Virtex-6 FPGAs will migrate easily to the Kintex-7, with similar performance, lower power and reduced price.

"Pico Computing is demonstrating technical leadership with the M-505 by pairing the Kintex-7 with their scalable FPGA board architecture. This is a low-power high-density high performance solution that outperforms many other HPC solutions including multi-core systems for integer applications that involve search and pattern matching operations,”  said Prasanna Sundararajan, Sr. Staff Systems Architect, HPC, at Xilinx.

The M-505 features a Xilinx Kintex-7 XC7K325T with one DDR3 SODIMM providing up to 12.8 GB/s of local memory bandwidth to the FPGA. Communication to the host is through x8 Gen2 PCIe. There are 34 LVDS and eight GTX transceivers on the M-505. The M-505 can also be configured independent of a host system, as a stand-alone module for embedded applications. The M-505 continues to follow Pico’s scalable architecture design; up to 6 modules can fit on an EX-500 PCIe backplane, allowing up to 48 FPGAs in Pico’s SC5 SuperCluster.

Pico Computing will demonstrate its M-505 module at the 2011 Supercomputing Conference (SC11) November 12 - 18, 2011 in Seattle, Washington. Production boards will be available in the 2nd quarter of 2012. Beta program opens Q1 2012.


About Pico Computing

Pico Computing, headquartered in Seattle, Washington, specializes in highly integrated hardware accelerator platforms based on Field Programmable Gate Array (FPGA) technologies. We are hardware and embedded software design experts with domain knowledge in applications that include cryptography, networking, signal processing, bioinformatics, and scientific computing. Visit for more info.


About Xilinx

Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit


Pico Computing Releases Embedded M-Series Module

--Modular FPGA board enables high--performance, memory intensive computing for embedded applications.

Seattle, WA – September 27, 2011 – Pico Computing today announces the release of a new M-Series Module, the M-504. An adaptation of the M-503, this new module addresses the ever-increasing demands for memory and I/O bandwidth in embedded systems. With the inclusion of 128MB NOR FLASH, the Virtex-6 FPGA can now be configured independently of a host system. This enables the M- 504 to be a stand-alone module for embedded applications such as medical imaging, signal processing, machine vision, and robotics.

The M-504 features a Xilinx Virtex-6 LX240T FPGA with 2 independent banks of DDR3 SODIMM providing 17GB/s of local memory bandwidth to the FPGA. In addition to the DDR3, there are 3 independent banks of QDRII SRAM capable of 10.8GB/s of sustained random access memory bandwidth. There is a single x8 Gen2 PCIe link, sixty-three (63) LVDS, and eight (8) GTX transceivers available via the Samtec QTH series connectors. The M-504 will also be available with Virtex-6 LX365T, LX550T, SX315T or SX475T FPGAs.

Like the M-503 before it, the M-504 can be used in conjunction with the EX-500 PCIe backplane as an HPC system. Thus Pico is able to “cluster” three M-504s per PCIe slot, or up to 24 in their SC5 SuperCluster 4U Chassis. As an embedded module the M-504 can be ruggedized for harsh environments and industrial temperature ranges.

Pico Computing will demonstrate its M-504 module at the International Conference for High Performance Computing 2010 (SC11) November 12 - 18, 2011 in Seattle, Washington.

About Pico Computing

Pico Computing, headquartered in Seattle, Washington, specializes in highly integrated hardware accelerator platforms based on Field Programmable Gate Array (FPGA) technologies. We are hardware and embedded software design experts with domain knowledge in applications that include cryptography, networking, signal processing, bioinformatics, and scientific computing. Visit for more info.



ALDEC Sponsors Advance Innovation Laboratory at TsingHua University and Research Center

HENDERSON, Nevada – November 17, 2010 – Aldec Inc., a leader in RTL Simulation and Electronic Design Automation (EDA), and TsingHua University in Beijing, one of the most renowned Chinese universities and research centers in Asia, signed an agreement to create an Advanced Innovation Laboratory. The laboratory will promote innovations in FPGA and SoC design projects.  The laboratory will also be serving as the educational center for FPGA design and EDA applications and support center for an annual pan-Asia electronic design competition.  TsingHua University will be providing workstations and network infrastructure for the lab and Aldec will supply Active-HDL a mixed HDL design creation and simulation software product that recently was awarded “2010 Best FPGA Development Tool” in China. For more


Aldec-Israel Established

HENDERSON, Nevada – November 8, 2010 – Aldec Inc., a leader in mixed RTL simulation and hardware assisted verification, announced the opening Aldec-Israel.  Mr. Uri Farkash has been appointed as country manager, AST for distribution of hardware verification products and Sital Technologies for distribution of software verification products.
Aldec is now positioned to better-serve its growing design and verification engineering customers and partner network in Israel. The office will be focused on sales, marketing and technical support for Aldec’s products in Israel.

"The opening of Aldec-Israel supports our global market expansion and is a vital landmark in the support of our overall growth strategy.  The office will setup a strong network for our customers and new FPGA and ASIC partners, as they continue to demand support for emerging verification methodologies” stated Stanley Hyduke, CEO of Aldec, Inc. For more


Impulse & Convey to Support C-to-FPGA for Accelerated Computing

 Bellevue, WA – November 5, 2010 – Impulse Accelerated Technologies today announced that the Impulse C-to-FPGA compiler will be extended to support Convey’s HC-1 Hybrid-Core server. The companies are collaborating to integrate the Impulse compiler into the Convey Personality Development Kit (PDK), allowing C-language algorithms to be deployed as FPGA hardware accelerators in high performance computing applications. For more



Trade Response Latency Reduced to Under Two Microseconds by Combining NASDAQ ITCH and OUCH into a Single FPGA

 Seattle, WA – September 15, 2010 – in-FPGA™ Trading Systems ( today announced a hardware-accelerated automated trading reference design that performs NASDAQ ITCH feed handling and outbound OUCH order entry running on 10Gb Ethernet, with under two microseconds of latency. The system is to be shown at the 2010 High Performance Computing Financial Markets show and conference, booth 424, in New York City on September 20th, 2010. For more



Aldec, HighRely and Leading FPGA Vendors Establish DO-254 Ecosystem

HENDERSON, Nevada –September 13, 2010 – Aldec, Inc. an EDA leader in FPGA and ASIC Verification and HighRely Inc., industry-leading DO-254/DO-178B avionics development and engineering services company, announce the establishment of a DO-254 ecosystem, including Aldec, HighRely and industry leading programmable logic vendors: Actel® (NASDAQ:ACTL), Altera® (NASDAQ:ALTR) and Xilinx® (NASDAQ:XLNX). Aldec and HighRely provide a comprehensive certifiable DO-254 solution which covers the entire front-end and back-end of DO-254 compliance requirements for any DO-254 program that requires in hardware programmable logic validation. Aldec DO-254 at-speed in-hardware verification solution has been adopted at five global avionics companies over the last nine months and helped those organizations achieve Level A and B compliance all of which included programmable logic devices. For more




ALDEC FPGA design verification system Active HDL is awardedto be the 2010 Best FPGA design tool in China FPGA Industry Development Forum

Guidance by the Ministry of Industry and Information Technology, organized by Xi'an Science and Technology Bureau, Xi'an IC industry development and China's electronic newspaper, co-organized by semiconductor industry associations of Shaanxi Province, Xi'an Software Park Development Center and Xi'an Science and Technology Exchange Center , "2010 (twith), China FPGA Industry Development Forum" held in Xi’an on August 31, 2010, ALDEC FPGA design verification system Active HDL is award the 2010 Best FPGA design tool. For more



 C-to-FPGA Integration Accelerates Prototyping 10X

 Bel Air, MD -- 31 August 2010 -- Stone Ridge Technology today announced integration to the popular Impulse C-to-FPGA toolset. The integration enables software developers to write HLL (high level language) algorithms that rapidly compile to optimized RTL (register transfer logic) targeting the Stone Ridge RDX-11 FPGA board and development kit. For applications with significant non-sequential logic the speed improvements can be 10 – 100x. Compared to hand coded RTL methodologies, the design entry can take two thirds the time and iterations one eighth the time. For more


Pico Computing Unveils FPGA Library for Signal Processing and Video Analytics

 Seattle, WA – July 26, 2010 – Pico Computing today announced the availability of its Signal Processing Library (SPL), a set of FPGA firmware components and related tools that speed the development and deployment of advanced video and network analytics for security, defense and aerospace applications. For more


Pico Computing Accelerates Cracking of NTLM Authentication Protocol

 Las Vegas, NV – July 26, 2010 – Pico Computing, the leading provider of hardware-accelerated cryptography solutions, announced today that it has successfully accelerated cracking of the NTLM (NT LAN Manager) authentication protocol, resulting in performance of over 144 billion keys per second using a cluster of 36 Xilinx FPGA devices installed in a single 4U system consuming under 1500 watts. This compares with typical performance of less than 20 million keys per second using a modern dual-core CPU, or 250 million keys per second when using a GPU-accelerated system. For more


VHDL IEEE 1076-2008 is Alive and Thriving

HENDERSON, Nevada—September 1, 2010 Aldec, Inc., a leader in mixed RTL simulation and verification, announces support for the VHDL IEEE 1076™-2008 standard. Aldec has a long history of VHDL support and over 44% of Aldec customers use the language today. Aldec is pleased to announce that VHDL IEEE 1076-2008 is alive and thriving, and is used by a growing percentage of Aldec design and verification customers. Implementation of the new version of VHDL standard is a vital part of the Aldec product offerings and the company pledges continual development of IEEE 1076-2008, and the future editions of the standard. For more


ARRIS Implements PDTi’s Register Management Web Application Tool

Vancouver, BC, June 23, 2010 — PDTi, an innovative provider of design automation products for hardware/software interface development, today announced that ARRIS, a global communications technology company, has selected and implemented PDTi’s state-of-the-art register management and collaboration tool to streamline FPGA design for ARRIS advanced broadband network hardware products. For more


PDTi now a Synopsys System-Level Catalyst Member

VANCOUVER, BC – (May 3, 2010) – PDTi, an innovative provider of design automation products for hardware/software interface development, today announced it has become a member of the Synopsys System-Level Catalyst Program, providing further integration and validation between SpectaReg, the industry’s leading register management and collaboration tool and a number of Synposys products including Innovator, Confirma and DesignWare. For more


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